The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 03, 2002
Filed:
Mar. 18, 1999
Stephen R. Schenck, McKinney, TX (US);
Bernhard H. Andresen, Dallas, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A clock multiplier ( ) comprises a digital phase lock loop circuit having a single variable delay stage ( ) for generating high and low phases for the output clocks. The variable delay stage ( ) includes a commutator which chooses between the signal propagating on first and second delay paths ( and ). The delay on the delay paths can be incrementally adjusted using capacitors ( and ) selectively enabled between the path and ground. If the variable delay is insufficient to lock the output to the reference clock, a prescaler ( ) automatically divides the output as needed. A stutter mode prevents short pulses, caused by a transition of the reference clock arriving shortly after the transition of the output clock to a low state, from being passed to the clock multiplying circuitry. The clock multiplier ( ) may use a free running mode after lock is obtained, where adjustments are made relative to the degree of difference between the output clock and the reference clock.