The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 03, 2002
Filed:
Apr. 09, 2001
Meng-Jer Wey, Hsinchu, TW;
Chu Yu Chin, Chu-Pei, TW;
Faraday Technology Corp., Hsinchu, TW;
Abstract
A programmable multi-configuration output buffer circuit having an input port terminal and an output port terminal. The output buffer circuit includes an output buffer stage having no delay unit and one or more output buffer stages having a delay unit. The output buffer stage having no delay unit includes a first type channel pull up transistor, a second type channel pull down transistor and a first logic circuit. The drain terminal of the first type channel pull up transistor and the second type channel pull down transistor are connected together and connected with the output port as well. The first logic circuit receives an enable signal and an input signal. The output buffer stage having a delay unit therein includes a first type channel pull up transistor, a second type channel pull down transistor and a second logic circuit. The drain terminal of the first type channel pull up transistor and the second type channel pull down transistor are connected together and connects with the output port as well. The second logic circuit is connected to the enable signal, the input signal and a corresponding select enable signal. The output buffer circuit may further includes a programmable storage unit for controlling output configuration. When the output buffer circuit is programmed, select enable signals can be outputted so that a portion of the output buffer stages having a delay unit can be triggered.