The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 03, 2002

Filed:

Jun. 06, 2000
Applicant:
Inventors:

Tushar R. Gheewala, Los Altos, CA (US);

Henry H. Yang, San Jose, CA (US);

Assignee:

In-Chip Systems, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/352 ;
U.S. Cl.
CPC ...
H01L 2/352 ;
Abstract

A user customizable integrated circuit architecture having separate regions for different types of core cells. In an embodiment of the present invention, all asynchronous core cells are placed in a first region and all synchronous core cells are placed in a second region thus allowing clock circuitry to be shared and clock traces to be efficiently routed. Clock buffers may also be placed in the second region. In a second embodiment, high-drive buffers are placed in the second region to enable efficient routing of high-drive power traces to the synchronous cells. Each region also may include metal programmable core cells that may be customized by the user for each design.


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