The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 03, 2002

Filed:

May. 17, 2000
Applicant:
Inventors:

Frank L. Thiel, Austin, TX (US);

William E. Moore, Round Rock, TX (US);

Philip S. Shiota, Sonoma, CA (US);

Assignee:

Legerity, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/7082 ; H01L 2/7102 ; H01L 2/970 ; H01L 3/111 ;
U.S. Cl.
CPC ...
H01L 2/7082 ; H01L 2/7102 ; H01L 2/970 ; H01L 3/111 ;
Abstract

A semiconductor process is disclosed which forms a field plate structure that integrally contacts an emitter region of a bipolar junction transistor by construction, without intervening interconnect layers or contacts. In one embodiment, a single-layer polysilicon electrode forms a field plate electrode which integrally interconnects to a traditional diffused emitter region formed before the polysilicon layer is deposited. This allows for deeper emitter regions required by the deep base regions needed for high-voltage bipolar devices. Moreover, the polysilicon layer, including the polysilicon electrode forming the field plate electrode, may be used as a local interconnect layer.


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