Method of synthesizing a cycle redundancy code generator circuit using hardware description language

Abstract

A method of synthesizing a CRC generator circuit for generating optimized code written in a high level hardware description language such as VHDL. The hardware description language code for implementing a CRC generator circuit has significantly less delay and utilizes fewer gates than prior art CRC generator circuit synthesis techniques. The method is operative to generate VHDL code which is then used to synthesize the circuit. The method iteratively generates the remainder equations for a CRC generator given the generator polynomial. During each iteration of the software, duplicate terms in each remainder equation are eliminated. The number of iterations is equal to the number of data bits the CRC generator is to process during each clock cycle. Once all the duplicate terms in the remainder equations are removed, the equations are sorted, rebuilt and translated into hardware description language code such as VHDL. The resulting optimized code may then be synthesized.