The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 27, 2002
Filed:
Jun. 12, 2001
Applicant:
Inventor:
Joseph J. Brehmer, Colorado Springs, CO (US);
Assignee:
LSI Logic Corporation, Milpitas, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract
An RTL back annotator for applying back annotated data to the RTL code of an RTL simulation for verifying actual timing performance for an ASIC array after layout during RTL simulation parses through annotation data from the back annotation file for the ASIC layout and generates RTL delays for each wire and register in the ASIC layout. The RTL annotator then applies the generated RTL delays to the RTL compiled design, thereby emulating the delays that a gate level netlist would have. In this manner, an RTL simulation having timings of the real layout may be run.