The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2002

Filed:

Mar. 15, 2000
Applicant:
Inventors:

Rajiv V. Joshi, Yorktown Heights, NY (US);

Karl E. Kroell, Altdorf, DE;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract

A computer program product method of circuit design of a multiple input circuit, macro or chip, especially for silicon on insulator (SOI) circuits. For a multiple input circuit, an object list of items corresponding to circuit devices is created. The items model local effects on corresponding circuit elements. The circuit is analyzed using Static or DC analysis to provide initial local effects on circuit devices, including body effects and local heat effects. The initial local effects are passed to the circuit model for transient analysis. The local effects from checked transient results are checked and updated. The transient response is rerun and the local effects are updated until the change in local effects is below an upper limit. For added efficiency, unswitching devices may be eliminated from the iterative analysis and analysis may be limited to the period when switching occurs.


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