Processor with different width functional units ignoring extra bits of bus wider than instruction width

Abstract

A data processing system contains a processor supporting both Narrow and Wide instructions and Narrow and Wide word size fixed-point and floating-point operands. The processor communicates over a bus utilizing a Wide word size with the remainder of the data processing system consisting of industry standard memory and peripheral devices. Narrow word sized instructions are stored on Wide word-sized storage devices. In a preferred embodiment, the processor bus has a first integer number of significant data lines. The processor is responsively coupled to the processor bus and includes a first decoder for decoding a first set of instructions received over the set of processor data lines, The first set of instructions each contains a second integer number, less than the first integer number, of significant bits. Fixed point arithmetic operations of a first class are performed in response to instruction decode by the first decoder on a first set of fixed point operands received over the set of processor data lines, wherein each of the first set of fixed point operands contains the second integer number of bits. Fixed point arithmetic operations of a second class are performed on a second set of fixed point operands received over the set of processor data lines, wherein each of the second set of fixed point operands contains the first integer number of bits. Corresponding processing is carried out in performing first and second classes of floating point operations.