Multiple low speed sigma-delta analog front ends for full implementation of high-speed data link protocol

Abstract

An analog front end (AFE) circuit used in a high-speed communications system is presented that includes multiple stages each including a bandpass filter, base band modulator, low pass filter and Sigma-Delta modulator. Each stage processes a fractional portion of the total frequency of a wide bandwidth analog signal. The number of such AFE stages is configurable in parallel to process the entire bandwidth of the received signal. The AFEs can be incorporated in a single integrated circuit or similar suitable manner so as to be modular, and easily replaceable/upgradeable. To achieve minimum quantization noise and reduce manufacturing costs, the Sigma-Delta modulators in each AFE are made to have identical characteristics. Because the wideband signal is broken down into smaller frequency portions, the sampling rate, and thus the complexity and cost associated with the AFEs, is reduced significantly. In a preferred embodiment, a number of such AFEs are used in an ADSL modem for processing separate but roughly equal portions of the wideband ADSL signal containing data carrying DMT sub-channels. The separated portions are re-combined in a DMT receiver logic circuit to reconstruct the original data stream.