The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2002

Filed:

Sep. 29, 1998
Applicant:
Inventor:

Bertrand DeBray, Maisons Laffitte, FR;

Assignee:

Alcatel, Paris, FR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04J 3/07 ;
U.S. Cl.
CPC ...
H04J 3/07 ;
Abstract

A method of inserting a service channel in frames that are plesiochronous relative to the service channel, the method including the steps of transmitting a block clock between a transmitter and a receiver of the frame, and reserving at the transmitter at least one location in the frames for the purpose of conveying the service channel data. The method further includes the steps of: inserting blocks (B) of the service channel into the reserved location causing each of the blocks (B) to be preceded by a predetermined number n of identical bits (D) referred to as “start” bits, and to do so in compliance with the following rules: in the event of there being no need to pad out the remainder of the location, repeating the method from the inserting step for a new block (B); in the event of it being necessary to pad out the remainder of the location, causing each of the blocks (B) to be followed by a number n of identical bits (F) referred to as “stop” bits, the “stop” bits (F) being different from the start bits (D), and repeating the method from the inserting step for a new block (B); and at the receiver: detecting the regular arrival of the start bits (D) or the regular arrival of the start bits (D) preceded by the stop bits (F), so as to be able to decide that the blocks (B) are present in the reserved locations and to extract the blocks (B) from the reserved locations.


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