The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2002

Filed:

May. 24, 1999
Applicant:
Inventors:

Ching Yu, Santa Clara, CA (US);

Xiaohua Zhuang, Santa Clara, CA (US);

Bahadir Erimli, Campbell, CA (US);

John M. Chiang, San Jose, CA (US);

Shashank Merchant, Sunnyvale, CA (US);

Robert Williams, Cupertino, CA (US);

Edward Yang, San Jose, CA (US);

Chandan Egbert, San Jose, CA (US);

Vallath Nandakumar, Campbell, CA (US);

Ian Lam, Daly City, CA (US);

Eric Tsin-Ho Leung, San Jose, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 5/22 ;
U.S. Cl.
CPC ...
H04L 5/22 ;
Abstract

A network switch having switch ports for full-duplex communication of data packets with respective network nodes according to Ethernet (IEEE 802.3) protocol that allocates a prescribed number of external memory bandwidth slots between high data rate ports based on the compared amount of network traffic on the respective ports. A scheduler within an external memory interface initially assigns memory access slots to the respective high data rate ports according to a prescribed sequence. If the scheduler subsequently detects that the network data traffic on a port having less slots is higher than the traffic on a port having more slots, the slots are swapped between the high data rate ports. Additionally, a clock multiplexer in one of the high data rate ports adjusts the data rate of the port dependent upon the number of slots assigned to that port. The swapping of bandwidth slots between the high data rate ports along with the adjustment of the port clock rate enables the efficient use of limited memory bandwidth resources.


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