The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 27, 2002
Filed:
Jun. 27, 2001
Applicant:
Inventor:
Shingo Hashimoto, Tokyo, JP;
Assignee:
NEC Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 1/1412 ;
U.S. Cl.
CPC ...
G11C 1/1412 ;
Abstract
A memory cell has a pair of n-ch drive MOS transistors, a pair of p-ch access MOS transistors. The access MOS transistor supply electric charge to storage nodes of the drive MOS transistors without using a resistive load. The gate insulation films of the drive MOS transistors have a thickness lower than the thickness of the gate insulation films of the access MOS transistors for achieving stable and high-speed operation of the memory cell.
Hashimoto, Shingo. (2002). Load-less four-transistor memory cell with different gate insulation thicknesses for n-channel drive transistors and p-channel access transistors (U.S. Patent No. 6442062). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6442062
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile