The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2002

Filed:

Sep. 13, 2000
Applicant:
Inventors:

Xingsheng Liu, Blacksburg, VA (US);

Guo-Quan Lu, Blacksburg, VA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 7/06 ;
U.S. Cl.
CPC ...
H05K 7/06 ;
Abstract

Resistance and parasitic inductance resulting from interconnection of semiconductor chips in power modules are reduced to negligible levels by a robust structure which completely avoids use of wire bonds through use of ball bonding and flip-chip manufacturing processes, possibly in combination with chip scale packaging and hourglass shaped stacked solder bumps of increased compliance and controlled height/shape. Turn-off voltage overshoot is reduced to about one-half or less than a comparable wire bond packaged power module. Hourglass shaped solder bumps provide increased compliance and reliability over much increased numbers of thermal cycles over wide temperature excursions.


Find Patent Forward Citations

Liu, Xingsheng. (2002). Low-cost 3d flip-chip packaging technology for integrated power electronics modules (U.S. Patent No. 6442033). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6442033

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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