The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 27, 2002
Filed:
Nov. 29, 2000
Applicant:
Inventor:
Yutaka Ikeda, Hyogo, JP;
Assignee:
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L 7/00 ;
U.S. Cl.
CPC ...
H03L 7/00 ;
Abstract
A DLL circuit includes a counter control circuit. The counter control circuit includes an inverter, a NAND gate, a shift register, a clocked inverter, and a NOR gate. When a reset signal RST of an H level, or a smallest address signal CMIN indicating the smallest value of the address is input, the counter control circuit forces a signal REV to be switched to an H level and generates a counter control signal ADD and a signal EN of an H level, whereby the counter enters a force up mode. As a result, the delay clock CLKD can be set in phase with a reference clock CLK stably.