Alignment mark fabrication process to limit accumulation of errors in level to level overlay

Abstract

A process for device fabrication, including coating a wafer with a layer including SiO , SiN , and a first resist, defining shallow trench isolation and alignment patterns in the first resist, transferring the first resist pattern into the SiO and SiN , removing the first resist, etching trenches to a depth suitable for shallow trench isolation, coating the wafer with a second photoresist, defining open areas around alignment-marks, etching alignment mark trenches to a depth greater than the trench depth, suitable for alignment mark detection, removing the second resist and the SiN , depositing SiO to fill the trenches for shallow trench isolation and partially fill the alignment mark trenches for alignment mark detection; and performing chemical mechanical polishing, leaving shallow trench isolation features and topographical alignment marks. As a result, alignment marks can be fabricated from the STI level with an arbitrary depth and an SiO fill to produce topography and/or material contrast without accumulating errors by using a mask that is separate from the transistor isolation feature mask to define the alignment mark positions.