The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2002

Filed:

Jun. 22, 2000
Applicant:
Inventor:

Yasuki Yoshihisa, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/18238 ;
U.S. Cl.
CPC ...
H01L 2/18238 ;
Abstract

A manufacturing method of a semiconductor device which can form high-performance bipolar transistors and high-performance MOS transistors on the same substrate while minimizing increases in the number of manufacturing steps and the number of masks. A base lead-out electrode of an NPN bipolar transistor and the gate of a PMOS transistor can be formed at the same time by using the same material (a polysilicon film ), and an emitter lead-out electrode of the NPN bipolar transistor and the gate of an NMOS transistor are formed at the same time by using the same material (a polysilicon film ). Therefore, a surface channel PMOS transistor can be obtained while an increase in the number of manufacturing steps is prevented. As a result, the leak current of the PMOS transistor can be reduced and the threshold voltage Vth can be controlled easily.


Find Patent Forward Citations

Yoshihisa, Yasuki. (2002). Manufacturing method of semiconductor device (U.S. Patent No. 6440787). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6440787

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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