High-level synthesis device high level synthesis method and recording medium with high level synthesis program

Abstract

A high-level synthesis device includes: a process extraction section for extracting an available process which performs data communications through a path having no loop from all processes described in an inputted behavioral description; a circuit synthesis section for producing partial circuits realizing the respective available processes and connecting the partial circuits in accordance with the inputted behavioral description so as to synthesize a circuit; and a delay insertion section for inserting a delay circuit in a path connecting partial circuits realizing the available processes so that data communications between the partial circuits through a plurality of paths are synchronized with each other. With the high-level synthesis device, it is possible to simulate synchronous communications between asynchronous processes in accordance with the inputted behavioral description including the description of the synchronous communications, and synthesize a circuit which has a small scale on the whole and operates at a high speed without providing control lines for handshaking.