The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 20, 2002
Filed:
Apr. 14, 1999
James Arthur Farrell, Harvard, MA (US);
Harry Ray Fair, III, Newburyport, MA (US);
Nevine Nassif, Arlington, MA (US);
Gill Watt, Acton, MA (US);
Compaq Computer Corporation, Houston, TX (US);
Abstract
A method and apparatus for determining load capacitance of DCVSL circuits in timing verification of a circuit is disclosed in the present invention. The gate capacitances for various MOS devices are modeled based upon simulations with certain conditions for inputs to the gate, source and drain. The system then determines the existence of DCVSL circuits within the topology of a circuit, and applies one of several models to determine minimum and maximum capacitances for the encountered DCVSL structures. The determination of minimum and maximum capacitance depends upon the selected model and the capacitance of each of the MOS devices as previously calculated.