The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2002

Filed:

Jul. 01, 1999
Applicant:
Inventors:

Richard William Doing, Rochester, MN (US);

Ronald Nick Kalla, Zumbro Falls, MN (US);

Stephen Joseph Schwinn, Lakeville, MN (US);

Edward John Silha, Austin, TX (US);

Kenichi Tsuchiya, Rochester, MN (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/206 ;
U.S. Cl.
CPC ...
G06F 1/206 ;
Abstract

A processor supports logical partitioning of a computer system. Logical partitions isolate the real address spaces of processes executing on different processors and the hardware resources that include processors. However, this multithreaded processor system can dynamically reallocate hardware resources including the processors among logical partitions. An ultra-privileged supervisor process, called a hypervisor, regulates the logical partitions. Preferably, the processor supports hardware multithreading, each thread independently capable of being in either hypervisor, supervisor, or problem state. The processor assigns certain generated addresses to its logical partition, preferably by concatenating certain high order bits from a special register with lower order bits of the generated address. A separate range check mechanism concurrently verifies that these high order effective address bits are in fact 0, and generates an error signal if they are not. In the preferred embodiment, instruction addresses from either active or dormant threads can be pre-fetched in anticipation of execution. In the preferred embodiment, the processor supports different environments which use the hypervisor, supervisor and problem states differently.


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