Correlator with serial-parallel partition

Abstract

A correlator and method of correlating include a circuit that serially receives in phase (I) and quadrature (Q) signal data along parallel I and Q signal channels at one input bit time periods and converts the data into blocks of n bit parallel I and n bit parallel Q signal data. A data bus receives the signal and reference data. A multiplexer is positioned in each of the n parallel paths extending from the data bus and receives the n bit parallel I and Q reference data and a one bit shifted version of the respective n bit parallel I and Q signal data from the adjacent previous path. Each multiplexer includes I and Q summed outputs based on the value of I and Q reference data on a bit-by-bit basis. An n bit Wallace Tree Adder is connected to each of the I and Q summed outputs for each multiplexer within each of the n parallel paths and computes a count based on the number of bits that are set out of n bits to form partial correlation products. An adder and accumulator register in feedback with the adder adds partial correlation products into a single sum. An output bus receives pairs of I and Q component signal outputs from the parallel paths one at a time at one input bit time periods such that there is one correlation product output for every I and Q pair of input bits.