Non-volatile memory, method of manufacture, and method of programming

Abstract

A semiconductor device includes a non-volatile memory, such as an electrically erasable programmable read only memory (EEPROM) array of memory cells. The memory is arranged as an array of cells in rows and columns. P-well regions of the array are spaced apart and electrically isolated by shallow trench features. The cells of each column are positioned within a respective isolated p-well region. Control gates of sequentially corresponding memory cells in columns of the array are electrically coupled by common wordlines. Bitlines electrically couple drain regions of each memory cell in the respective columns of the memory cell array. Source lines electrically couple source regions of each memory cell in the respective columns of the array. The source lines and at least one memory cell in each column of the array are electrically coupled to the p-well region corresponding to the column of the source line and cell. Each column of the array is therefore located within an isolated well, common to the cells in the column but isolated from other wells of other columns. The array is programmed by pulsing potentials as to each column, with isolation of results for each column.