The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 20, 2002
Filed:
Dec. 19, 2000
James A. Antone, Austin, TX (US);
Melvin W. Stene, Pocatello, ID (US);
Brian R. Kauffmann, Pocatello, ID (US);
AMI Semiconductor, Inc., Eastlake, OH (US);
Abstract
A delay lock loop circuit is disclosed which includes a delay block which receives the clock signal and delays the clock signal by a selected amount to generate the delayed clock signal. A phase detector receives the clock signal and the delayed clock signal, compares the phases of the two signals and generates a phase comparison signal. A lock detector receives the clock signal and the delayed clock signal, compares the timing of the two signals and generates a potential lock indication signal. A controller receives the phase comparison signal and the potential lock indication signal and provides a delay control signal to the delay block to change the selected delay amount in response to the phase comparison signal. The controller interrupts the clock signal to the delay block for a selected interval in response to the potential lock indication signal, and generates a true lock indication signal in response to the potential lock indication signal after the interruption of the clock signal to the delay block. The delay lock loop circuit is capable of handling a wide range of clock frequencies and a step increase or decrease in the clock frequency.