The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 20, 2002
Filed:
Dec. 29, 2000
Sung Kwon Lee, Seoul, KR;
Hynix Semiconductor, Inc., , KR;
Abstract
A method for manufacturing a semiconductor device is provided which suppresses migration of lower interconnectors formed on a borophosphosilicate glass (BPSG) layer toward upper interconnectors as a result of secondary reflowing of the BPSG layer during subsequent thermal processing, thereby preventing the formation of electrical shorts. The semiconductor device manufacturing method includes: forming a transistor; depositing a first interlevel dielectric film (ILD) to cover the transistor; depositing a BPSG layer as a planarization layer on the first interlevel dielectric film; reflowing the BPSG layer; etching the BPSG layer using Ar ion sputtering until a portion of the film is exposed, thereby planarizing the surfaces of the first ILD and the BPSG layers forming an interconnector on the exposed portion of the first interlevel dielectric film; depositing a second interlevel dielectric film to cover the interconnector and the BPSG layer; and forming metal electrodes on the second interlevel dielectric film, the metal electrodes being in contact with predetermined regions of the transistor.