The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2002

Filed:

Jun. 20, 2001
Applicant:
Inventors:

Tae Kyun Kim, Kyoungki-do, KR;

Se Aug Jang, Kyoungki-do, KR;

In Seok Yeo, Seoul, KR;

Assignee:

Hynix Semiconductor, Inc., Kyoungki-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1336 ;
U.S. Cl.
CPC ...
H01L 2/1336 ;
Abstract

The MOSFET fabrication method allows application of a self-aligned contact (SAC) process while maintaining a metal gate, such as a tungsten gate, to have a uniform thickness. The process involves forming a metal oxide film during the formation of a metal gate structure of the MOSFET device. The metal oxide film is formed by subjecting the gate structure through a rapid thermal oxidation (RTO) treatment and then to an N O plasma treatment. The treatments allow the thickness of the metal oxide to be precisely controlled. The metal oxide acts as an insulator, which prevents electrical shorts between the gate structure and a contact plug even if a misalignment of occurs during the SAC process. This is an improvement from the conventional practice of separately forming a SAC barrier film after the formation of the metal gate structure and thus saves money, time, and increases reliability and productivity. Also the performance characteristics of the device is enhanced.


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