The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 13, 2002
Filed:
May. 26, 1999
John G McBride, Ft Collins, CO (US);
Thomas N Indermaur, Denver, CO (US);
Hewlett-Packard Company, Palo Alto, CA (US);
Abstract
The present invention is generally directed to a system and method for evaluating a very large scale integrated circuit design in a structured, hierarchical fashion. In accordance with one aspect of the invention, a method evaluates a first circuit portion for a variety of potential errors and generates a first list of potential errors identified in the first circuit portion. The method further includes the step of adding at least one of the potential errors to a waiver file. The method further includes the step of examining a second circuit portion for a variety of potential errors, except those errors listed in the waiver file. In one embodiment, the step of examining the second circuit portion may be executed in a variety of ways. In one embodiment, the step may be configured to evaluate the second circuit portion for a number of potential errors. For any error(s) so identified, the method may add the errors to an error listing that is to be reported. However, the method may then exclude or omit from this listing any errors (or tests) listed in a waiver file. An associated system is also provided.