Low phase jitter clock signal generation circuit

Abstract

A direct digital synthesis (DDS) clock generation circuit ( ) produces a digital clock signal having low phase jitter. A N/M digital divider circuit ( ) produces an output signal having a frequency of N/M times an input clock frequency. The N/M digital divider ( ) generates a control signal that is used to alternately charge and discharge a capacitor ( ) through a current source ( ) and a current sink ( ) to produce a linear sawtooth waveform having rising and falling rates which are proportional to the N and M−N values, respectively. A voltage sensor and current controller ( ) automatically adjust the current sink ( ) and current source ( ) to maintain waveform amplitude at a relatively constant magnitude and average DC level. A voltage comparator ( ) compares the instantaneous voltage on the capacitor ( ) to a bias voltage and produces the digital clock signal having low phase jitter without the use of a sine look-up table, a digital-to-analog converter, or an analog filter.