Methods for improving the efficiency of clock gating within low power clock trees

Abstract

Methods are provided for improving the efficiency of clock gating within low power clock trees. In a first aspect, a correlation level between a plurality of clock gating signals and their corresponding gates which gate a source clock is determined. The clock gating signals and their corresponding gates are combined into a single clock gating signal and a single corresponding gate if a preselected level of correlation exists therebetween. In a second aspect, an area overlap is determined for a plurality of sinks, and one of the gated drovers of the sinks is removed. The sinks of the removed gated driver then are connected to a remaining gated driver driven by a single clock gating signal and a single corresponding gate. In a third aspect, physically proximate sink clusters are rewired to generate a pure clock gating group within each sink cluster if rewiring the clusters increases wiring length by less than a predetermined amount. In a fourth aspect, a clock gating group is selected and the power dissipation is computed for all sinks within the selected group assuming all the sinks therein are wired without clock gating. The power dissipation also is computed assuming all the sinks therein are gated. If the power dissipation for all sinks within the selected group is reduced by individually wiring the sinks therein, the group is ungated. A computer program product also is provided having a computer readable medium with means for performing the first, second, third and/or fourth aspects of the invention.