Multiport memory architecture with direct data flow

Abstract

The present invention provides a high speed, multi-ported, direct data flow memory architecture that employs memory width and speed greater than system bus width and speed to allow shallow burst depth and reduce other-port latencies, while maintaining multi-port throughput. The inventive system has a data storage device (SDRAM) and a multiplexer connected to the SDRAM. Two or more interfaces or ports are provided with data sourcing controllers respectively connected to the interfaces. A communications bus connects the SDRAM to the data sourcing controllers for facilitating data communications. A FIFO buffer memory is located between the multiplexer and the data sourcing controllers. The need for retries is eliminated and host bus widths are matched to memory data width. Read-ahead algorithms are provided that adapt the larger system bus burst sizes to the smaller memory burst sizes with the ability to cancel unneeded advance requests for data. The total memory bandwidth is greater than that of the sum of the ports, so that the small memory burst size inefficiency does not reduce throughput below target levels. Write data is selectively masked to eliminate the need for read-modify-write cycles. Reads and writes can begin and end on arbitrary byte addresses, regardless of memory or bus widths.