The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 13, 2002
Filed:
Sep. 20, 2000
Jeff S. Brown, Fort Collins, CO (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A method and apparatus for accommodating irregular memory write word widths allow for writing to multiple rows in a memory so as to reduce or eliminate holes in the address read space. First and second memory blocks are provided that include a first bitcell selectable by a first write bitline and a second bitcell selectable by a second write bitline. Where a write word width is not equal to a read word width and is not some factor of a power of two times the read word width, the column decode to read out the entire word is not a power of two, and holes in the read address space will exist. When the write address is even, a first range of bits is written to the first block on a first write bitline, a second range of bits is written to the second block on the first write bitline, and a third range of bits is written to the first block on a second write bitline. When the write address is odd, a first range of bits is written to the second block on the first write bitline, a second range of bits is written to the first block on the first write bitline, and a third range of bits is written to the second block on the second write bitline. Reading of data from the memory occurs as with a typical memory structure.