The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 13, 2002
Filed:
May. 28, 1999
Michael L. Haupt, Roseville, MN (US);
Mitchell A. Bauman, Circle Pines, MN (US);
Unisys Corporation, Blue Bell, PA (US);
Abstract
A memory request management system for use with a memory system employing a directory-based cache coherency scheme is disclosed. The memory system includes a main memory coupled to receive requests from multiple cache memories. Directory-based logic is used to determine that some requests presented to the main memory can not be completed immediately because the most recent copy of the requested data must be retrieved from another cache memory. These requests are stored in a temporary storage structure and identified as “deferred” requests. Subsequently, predetermined ones of the memory requests that are requesting access to the same main memory address as is being requested by any deferred request are also deferred. When a data retrieval operation is completed, an associated request is designated as undeferred so that processing for that request may be completed, and the request may be removed from the temporary storage structure. According to one aspect of the invention, all deferred requests requesting access to the same main memory address are stored as a linked list of requests in the temporary storage structure. Requests are processed by main memory in a first-in, first-out manner such that the oldest requests are completed before more recently-received requests. According to another aspect of the invention, the request management system further handles I/O overwrite operations wherein a peripheral device is allowed to overwrite requested addresses within the main memory even though the most recent copy of the data associated with some of the overwritten memory addresses is stored within ones of the cache memories. To process the I/O overwrite operations in a manner that preserves data coherency, the I/O overwrite requests are deferred in a manner that is similar to cache-initiated requests. Specifically, I/O overwrite requests made to an address associated with any previously-deferred I/O overwrite or cache-initiated requests are deferred until all such previously-deferred requests are processed by main memory.