Binary counter with low power consumption

Abstract

Disclosed is a novel n-bit binary counter with low power consumption, which comprises a set of half-adders for adding a “1” to an n-bit input signal, which includes a lower-order m bit component and a higher-order (n−m) bit component, and a set of D (data) flip-flops for storing outputs of the half-adders. The set of half-adders are divided into two sections, one of which is a first adder section for adding a “1” to the lower-order m bit component and the other of which is a second adder section for adding a carry signal from the first adder section to the higher-order (n−m) bit component. The set of D flip-flops are divided into two sections, one of which is a first register section to store outputs of the first adder section and the other of which is a second register section to store outputs of the second adder section. The n-bit input signal is comprised of the outputs of the first and second register sections. The novel n-bit binary counter further comprises a clock gating circuit which allows the second register section to store the outputs of the second adder section only when the carry signal of “1” is generated from the first adder section. Since D flip-flops of the second register section are not toggled until the carry signal of “1” is generated from the first -adder section.