Dual fragment-cache pixel processing circuit and method therefore

Abstract

A dual-cache pixel processing circuit that allows one cache to be flushed while the other receives subsequent pixel fragments is presented. The system includes a first fragment cache and a first set of state registers where the first set of state registers stores state variables for drawing operations corresponding to fragments stored in the first fragment cache. The system also includes a second fragment cache and a second set of state registers where the second set of state registers stores state variables for drawing operations corresponding to fragments stored in the second fragment cache. The system further includes a render backend block that is operably coupled to the first and second fragment caches and to a frame buffer that stores current pixel information for a plurality of pixels in a display frame. The render backend block combines fragments received from the first and second caches with portions of the current pixel information in the frame buffer to produce revised pixel information that is stored back in the frame buffer. The combination operations performed by the render backend block utilize the state information stored in one of the first and second sets of state registers based on from which fragment cache the fragment being combined originated. A control block that is operably coupled to the first and second fragment caches and the first and second sets of state registers initially routes received fragments to the first fragment cache. When a state change occurs, the control block alters the flow of fragments such that subsequent fragments are routed to the second fragment cache while the first fragment cache is flushed. Flushing the first fragment cache includes providing all of the pixel fragments included in the first fragment cache to the render backend block along with the old state variables that are stored in the first set of state registers.