The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 13, 2002
Filed:
Jun. 30, 1999
Applicant:
Inventors:
Craig Stevens, Ben Lomond, CA (US);
Tony Jakubiec, San Jose, CA (US);
Assignee:
Novellus Systems, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B65G 4/700 ;
U.S. Cl.
CPC ...
B65G 4/700 ;
Abstract
A wafer processing system includes a single-wafer load lock with integrated cooling unit. The small volume of the single-wafer load lock allows for fast pump down and vent cycles. By integrating a cooling unit within the load lock, system throughput is further increased by eliminating the need to move a newly processed wafer to a separate cooling unit before moving the wafer to the load lock.
Quick Actions:
Stevens, Craig. (2002). Wafer processing architecture including single-wafer load lock with cooling unit (U.S. Patent No. 6431807). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6431807
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile