Memory device for constituting a memory subsystem of a data processing apparatus

Abstract

In a memory device capable of processing a small amount of data in a high speed, this memory device is suitable for various sorts of systems in which a plurality of access requests for continuous addresses are mixed with each other, and are issued as irregular requests to a memory subsystem. A data array is provided in a memory device having a memory cell. This data array may be arranged as a virtual register array having an arbitrary number of arbitrary word length. The data register array is accessed by employing a virtual register number and a virtual word number, which are supplied from an external circuit provided outside the memory device. In the memory device, both the virtual register number and the virtual word number, which are supplied from the external circuit, are converted into both an absolute register number and an absolute word number by an internally-provided converting circuit so as to access the data register array. With employment of such an arrangement, the respective structures of the data register array are separately optimized with respect to different application programs, so that accessing efficiencies can be improved.