The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 2002

Filed:

Aug. 02, 2001
Applicant:
Inventor:

Jiann-Ming Shiau, Nantou, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 1/700 ;
U.S. Cl.
CPC ...
G11C 1/700 ;
Abstract

A flat memory cell read only memory is disclosed. A flat cell ROM array is formed on a substrate. This array is formed by a plurality of sub-arrays. In each sub-array, a plurality of first buried diffusion regions are planted into the substrate. A insulating layer covers on the substrate. A plurality of wordlines and metal bitlines are formed on the insulating layer. The wordlines are vertically buried to the diffusion region. A flat FET array is installed in a section between the lower sides of two adjacent buried diffusion regions and word lines. Four block selecting lines are used to control the selection of the memory cell selecting transistors for reading a selecting memory cell. Commonly used metal bitlines and transistors of a minimum number are used to read data. Therefore, it has the advantages of rapidly reading, small size, high density and lower power consumption.


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