The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 06, 2002
Filed:
Jan. 16, 2001
Hironori Iga, Hyogo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
An input buffer of a signal level conversion circuit according to the present invention includes: a differential amplification circuit of a current mirror amplifier amplifying a potential difference of first and second nodes respectively supplied with an external signal and a reference signal for outputting an internal signal; and a bias circuit applying the same bias potential to the first and second nodes. The bias potential is set in such a way that potentials at the first and second nodes are set to a level where a group of transistors forming the current mirror amplifier can operate in a saturation region regardless of the levels of the external signal and the reference signal.