The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 2002

Filed:

Jan. 24, 2000
Applicant:
Inventors:

Fujio Ishihara, Tokyo-To, JP;

Yukihiro Urakawa, Kawasaki, JP;

Yukihiro Fujimoto, Yokohama, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 1/900 ;
U.S. Cl.
CPC ...
H03K 1/900 ;
Abstract

A semiconductor integrated circuit device comprises: a clock driver for outputting a clock signal; a clock wiring which is driven by the clock driver for transmitting the clock signal; a plurality of logic circuits which are connected to the clock wiring to be synchronously operated in response to the clock signal; and a plurality of delay circuits, each of which is provided between a corresponding one of the logic circuits and the clock wiring for delaying the clock signal, wherein a delay amount of each of the delay circuits is designed so that the delay amounts of the clock signal from the output of the clock driver to the inputs of the logic circuits are equal to each other. Thus, it is possible to reduce clock skew and to evade an increase in layout area.


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