Low-power cmos device and logic gates/circuits therewith

Abstract

An insulated gate field effect transistor or a CMOS pair of transistors of a family of logic circuits includable in any type of integrated circuit, including microprocessors, memories and logic macros, and any or all functional portions thereof preferably forms an asymmetrical conduction device junction integrally with the gate structure to provide hysteresis that yields increased noise immunity and reduced power consumption and dissipation by asymmetric alteration of switching thresholds for positive and negative input signal transitions such that the turn-ON transition time or speed is slowed relative to the turn-OFF transition time or speed. The asymmetric conduction function is preferably provided by a polysilicon diode junction which is exposed and allowed to function as such by masking prior to application of a conductive material to the gate structure.