The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 2002

Filed:

Sep. 15, 1999
Applicant:
Inventors:

Rolf Magnus Berggren, Linköping, SE;

Bengt Goran Gustafsson, Linköping, SE;

Johan Roger Axel Karlsson, Linköping, SE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/184 ; H01L 2/9786 ;
U.S. Cl.
CPC ...
H01L 2/184 ; H01L 2/9786 ;
Abstract

A field-effect transistor is made with electrodes ( ) and isolators ( ) in vertically provided layers, such that at least the electrodes ( ) and the isolators ( ) form a step ( ) oriented vertically relative to the first electrode ( ) or the substrate ( ). Implemented as a junction field-effect transistor (JFET) or a metal-oxide semiconducting field-effect transistor (MOSFET) the electrodes ( ) forming respectively the drain and source electrode of the field-effect transistor or vice versa and the electrode ( ) the gate electrode of the field-effect transistor. Over the layers in the vertical step ( ) an amorphous, polycrystalline or microcrystalline inorganic or organic semiconductor material is provided and forms the active semiconductor of the transistor contacting the gate electrode ( ) directly or indirectly and forming a vertically oriented transistor channel ( ) of the p or n type between the first ( ) and the second ( ) electrode. In a method for fabrication of a field effect transistor a vertical step ( ) is formed by a means of a photolithographic process and a soluble amorphous active semiconductor material ( ) is deposited over the first electrode ( ) and the vertical step ( ) such that a vertically oriented transistor channel between the drain and source electrode ( ) is obtained. In a JFET the semiconductor material ( ) contacts the gate electrode ( ) directly. In a MOSFET a vertically oriented gate isolator ( ) is provided between the gate electrode ( ) and the semiconductor material ( ).


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