Integrated-circuit manufacturing using high interstitial-recombination-rate blocking layer for source/drain extension implant

Abstract

In the fabrication of a 0.10 micron CMOS integrated circuit, a high-energy plasma etch is used to pattern a polysilicon layer and an underlying gate oxide layer to define gate structures. A thermal oxide step anneals silicon exposed and damaged by this etch. Instead of using this thermal oxide as a blocking layer for a source/drain extension implant, it is removed so as to expose the silicon surfaces of the source/drain regions. A TEOS deposition results in a carbon-bearing silicon dioxide layer in contact with the surfaces of the crystalline source/drain regions. A boron PMOS source/drain extension implant is performed through this carbon-bearing blocking layer. Subsequent steps result in the formation of sidewall spacers, heavily doped source/drain sections, submetal dielectric, an intermetal dielectric interconnect structure, and passivation. The relatively high interstitial recombination rate of the carbon-bearing blocking layer attracts a flow of interstitial silicon. This flow draws some of the boron extension implant with it—effectively limiting the depth and lateral extension (under the gate) of the boron. This, in turn, helps limit the short channel effect, and yields a more reliable 0.1 micron PMOS transistor.