The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 2002

Filed:

May. 24, 2001
Applicant:
Inventors:

Dale A. Gee, Los Gatos, CA (US);

Abhijeet D. Sathe, Tracy, CA (US);

Assignee:

Nayna Networks, Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/100 ;
U.S. Cl.
CPC ...
H01L 2/100 ;
Abstract

A method for fabricating a mirror array from a silicon on insulator substrate structure. The method includes providing a silicon-on-insulator (SOI) substrate structure, which may have a material thickness of greater than 10 microns overlying an insulating layer. The SOI material thickness is of a single crystal silicon bearing material. The method also patterns the material thickness using a deep reactive ion etching process to pattern a mirror device structure by forming a trench region that extends from a surface of the material thickness to the insulator structure; and patterns the thickness of material to form a recessed region coupled to the trench region to define a torsion bar structure. The recessed region extends from the surface of the material thickness and is less than about 80% of the mirror device thickness. The method forms an opening on a back side of the SOI substrate structure to the insulator structure. The method removes the insulator material to release the mirror device structure and the torsion bar structure.


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