Method for efficient verification of system-on-chip integrated circuit designs including an embedded processor

Abstract

A method for using verification software for testing a system-on-chip (SOC) design including an embedded processor. The verification software is used to generate and apply test cases to stimulate the SOC design in simulation; the results are observed and used to de-bug the design. Verification of a SOC design which includes an embedded processor is typically very slow. To provide for a speed-up mode of verification in such a case, in the method of the present invention, verification software is partitioned into higher-level control code and lower-level device driver code. The higher-level code performs such functions as decision-making, test initialization, test randomization, multi-tasking, and comparison of test results with expected results. The low-level code interfaces with a core being simulated, to apply the test case generated by the upper-level code on a hardware level of operations. The partitioning of the verification software as described above allows for a “split-domain” mode of verification in which only the low-level code is executed by a simulated processor model, while the rest of the code executes externally to the simulator. Because most of the verification software executes externally to the simulator while only the low-level code executes on the simulated processor, the overhead of performing the high-level functions is removed from the simulator. As a result, faster verification is enabled.