Digital signal processor and processor reducing the number of instructions upon processing condition execution instructions

Abstract

In a digital signal processor for pipeline processing divided into at least three steps, i.e., instruction fetch cycle, instruction decode cycle and instruction execution cycle, a value of a register (A) is put on a data bus assuming the condition is consistent when a condition execution instruction is decoded in an instruction decoder ( ). Then, in the instruction execution cycle of the condition execution instruction, a register (B) introduced the value on the data bus when upon consistency of the condition. As a result, even before a condition flag (Z) changes as a result of execution of the instruction for generating the condition in the instruction execution cycle, the condition execution instruction can be decoded. Thus, the processor may omit an instruction other than “condition generation instruction or condition execution instruction” which was conventionally required.