The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 30, 2002
Filed:
Sep. 21, 1998
James S. Roberts, Austin, TX (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A microprocessor capable of caching victimized branch prediction information is disclosed. Branch prediction information is generated as branch instructions are executed over time. This prediction information is stored in a branch target buffer. The storage locations within the branch target buffer correspond to cache line locations within the microprocessor's instructions cache. Instead of discarding branch prediction information corresponding to instructions that are replaced or discarded from the instruction cache, the branch prediction information is stored in a victim branch prediction cache. Address information may also be stored to identify which instructions the prediction information corresponds to. The microprocessor's instruction cache is configured to receive and store instruction bytes, and the branch target array is coupled to the instruction cache and configured to store branch target information corresponding to the stored instruction bytes. The branch target array is configured to output the stored branch target information to the victim branch prediction cache when the corresponding instruction bytes are no longer stored in the instruction cache. The victim branch prediction cache may be located within the microprocessor, in an external level two cache, or in a separate stand alone memory. Different schemes for generating the branch prediction information may be used. A computer system and method for caching victimized branch prediction information are also disclosed.