Arithmetic unit, digital signal processor, method of scheduling multiplication in an arithmetic unit, method of selectively delaying adding and method of selectively adding during a first or second clock cycle

Abstract

An arithmetic unit configured to perform multiply and add operations on three operands A, B and C, where A is the multiplicand, B is the multiplier and C is the addend. The arithmetic unit includes a multiplier unit having an input stage configured to receive operands A and B from a data pump and includes an output to provide a product AB. The arithmetic unit also includes a register having an input coupled to the multiplier unit output and an output and a multiplexer having a first data input coupled to the multiplier unit output, a second data input coupled to the register output, a toggle command input and a data output. A bypass decision block in the arithmetic unit includes an input stage configured to receive the operands A and B and includes an output coupled to a scheduler and to the toggle command input. The bypass decision block is configured to set the multiplexer to couple the first data input to the data output when most significant bits of the operands A and B have values below a first threshold. The arithmetic unit also includes an adder having a first data input coupled to the multiplexer data output configured to receive the product AB, a second data input configured to receive the addend C and an output to provide an output signal AB+C.