The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 30, 2002
Filed:
Jan. 26, 2001
Eric Jasinski, Colchester, VT (US);
Douglas W. Kemerer, Essex Center, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A memory cell layout provides for sharing of power supply connections between adjacent rows and columns of a memory array, respectively by providing a subarray layout in which one power connection is serpentine, extending into adjacent rows, and another stitches together a connection of memory cells in adjacent columns and adjacent rows. The subarray layout may be expanded by reflection and produced by lithographic exposures of relatively large numbers of memory cells in a step-and-repeat fashion. The layout of the power connections to the memory cells allows a significant reduction in the number of power connections required and/or the provision of redundant connections and a shielding mesh without increase of the number of connections required as well as full exploitation of minimum feature size with increased manufacturing yield.