The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 30, 2002

Filed:

Aug. 01, 2000
Applicant:
Inventor:

Takashi Fujiwara, Yokohama, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/08 ;
U.S. Cl.
CPC ...
H03K 5/08 ;
Abstract

In a suppresser circuit, a first voltage-to-current converting circuit converts an input voltage signal to an output current signal. A second voltage-to-current converting circuit has a non-inverting input terminal for receiving a predetermined bias potential and an inverting input terminal for receiving the input voltage signal. A current-limiting element is connected between the first and second voltage-to-current converting circuits, for substantially stopping a flow of current between the first and second voltage-to-current converting circuits while the input voltage signal remains at a level equal to or lower than the bias potential, and for decreasing the output current of the first voltage-to-current converting circuit while the input voltage signal remains at a level higher than the bias potential.


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