Twisted-ring oscillator and delay line generating multiple phases using differential dividers and comparators to match delays

Abstract

A phase-locked loop (PLL) or a delay-locked loop (DLL) has differential delay stages with differential outputs driving differential clock inputs to a pair of differential toggle flip-flops. One flip-flop changes state on the rising edge and the other on the falling edge of the true output from the delay stage. Differential-to-single-ended buffers convert differential flip-flop outputs to single-ended multi-phase clocks. To avoid erratic or multiple oscillation and overtones, fewer than eight and preferably four differential delay stages are used. The delay stages are arranged in a twisted-ring with the differential outputs of the last delay stage crossed over and fed back to the differential inputs of the first delay stage. Tail currents of the delay stages can be adjusted by a voltage generated by a PLL loop. The differential toggle flip-flops allow for many taps or clock phases to be generated from the few delay stages.