Area efficient delay circuits

Abstract

The present invention provides a library of cells that can be stored in a computer readable memory and used in the computer-aided design of integrated circuits. Some of the cells in this cell library describe circuits having variable delays. In this cell library, two different cells are able to represent circuits that can be configured to delay signal transmission by different time periods while still being contained within substantially equal areas on a silicon substrate. One way that the cell library allows for such a configuration is if the two cells both represent a delay circuits that contains an n-channel transistor coupled to a p-channel transistor. Each n-channel and p-channel transistor has an n- or p-channel gate respectively, and this gate can be described as having a length and a width. When the length of the n-channel gate in the first delay circuit differs from the length of the n-channel gate in the second delay circuit, the delay time associated with each circuit will also differ. For example, if the length of the n-channel gate in the first circuit is longer than that of the n-channel gate in the second circuit, the first circuit can have a longer delay than the second. Furthermore, the cells may also represent a delay circuit that has a capacitor coupled to the n- and p-channel transistors. If so, the delay of the circuit can be further modified by changing the size of this capacitor. These changes in n-channel gate length and capacitor size can be made while still occupying an area on the silicon substrate that is equal or substantially equal to the area occupied by the unchanged circuit. Alternately, the library could allow designers to modify the cells such that the circuits represented by the cells differ in delay time periods and occupy areas on the substrate that differ in breadth but not in height.