Snoopy test access port architecture for electronic circuits including embedded core with built-in test access port

Abstract

This invention is a testing technique for an electronic circuit such as an integrated circuit. The electronic circuit includes a JTAG test access port and at least one testable embedded core circuit having its own JTAG compliant second test access port. A test access port controller and a programmable switch control testing of the electronic circuit. An internal state in the test access port controller controls the switch state of the programmable switch. The programmable switch is controlled to selectively connect the first test access port to the embedded core circuits. When an embedded core circuit is connected for test, the test access port controller remains responsive to the first test access port and operates in a set of snoopy states corresponding to the state of the embedded core circuit under test. The test access port controller can regain control of the first test access port and disconnect all of the embedded core circuits when in snoopy states. The electronic circuit may include a non-testable embedded core circuit whose test is controller by the test access port controller.